This application claims the benefit of Korean Patent Application No. 2001-6215, filed on Feb. 8, 2001, and the benefit of Korean Patent Application No. 2001-55593, filed on Sep. 10, 2001, under 35 U.S.C. xc2xa7119, the entirety of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a non-volatile memory device, and more particularly, to an EEPROM cell and a method of manufacturing the same.
2. Description of Related Art
An electrically erasable programmable read only memory (EEPROM) is a device in which electrons move through a tunnel oxide film made of a thin insulating layer such as SiO2 by a Fowler-Nordheim (FN) tunneling phenomenon so that charges are stored in a floating gate, and a transistor is turned on or off according to an amount of charge accumulated in the floating gate. Whether the transistor is turned on or off depends on the magnitude of a threshold voltage of the device.
The EEPROM has become smaller in unit cell size as memory capacity has increased. If the size of a unit cell is reduced in order to satisfy this memory capacity requirement, there occurs a problem in that memory cell characteristics tend to deteriorate.
FIG. 1 is a cross-sectional view illustrating a floating gate tunnel oxide (FLOTOX) type of EEPROM cell according to conventional art. The EEPROM cell includes a semiconductor substrate 10. Even though not shown in FIG. 1, the semiconductor substrate 10 includes an active region and a field region. A tunnel insulating film 15 is formed on the active region of the semiconductor substrate 10 to a relatively thin thickness. A gate insulating film 17 is formed on a remaining portion of the active region of the semiconductor substrate 10 to a thickness thicker than the tunnel insulating film 15, except at a portion of the active region of the semiconductor substrate 10 on which the tunnel insulating film 15 is formed.
A floating gate 21, an interlayer insulator 22 and a sense line 23 are stacked on the tunnel insulating film 15 and the gate insulating films 17 interposing the tunnel insulating film 15 therebetween in the above-described order. The floating gate 21, the interlayer insulator 22 and the sense line 23 form a gate of a memory transistor 20. A word line 25 is formed on the gate insulating film 17 spaced apart from the memory transistor 20 to form a gate of a select transistor 30.
Spacers 18 are formed on both side walls of the floating gate 21 and the sense line 23 and on both side walls of the word line 25.
A channel region 40 is formed in a portion of the semiconductor substrate 10 under the tunnel insulating film 15 to overlap the word line 25. The channel region 40 includes an n+-type high-density doped region 31 and an n31 -type low-density doped region 35. At this point, the high-density doped region is referred to as a region having a relatively high impurity concentration, and the low-density doped region is referred to as a region having a relatively low impurity concentration.
A common source region 50 is formed in a portion of the semiconductor substrate 10 spaced apart from the channel region 40 to overlap the floating gate 21 of the memory transistor 20. The common source region 50 has a double diffusion structure of an n+-type high-density doped region 32 and an nxe2x88x92-type low-density doped region 36.
A drain region 60 is formed in a portion of the semiconductor substrate 10 spaced apart from the channel region 40 to overlap the word line 25. The drain region 60 has a double diffusion structure of an n+-type high-density doped region 33 and an nxe2x88x92-type low-density doped region 37.
In the conventional EEPROM cell of FIG. 1, the common source region 50 and the drain region 60 which have such a double diffusion structure are formed in accordance with the following. The nxe2x88x92-type low-density doped region 35, the nxe2x88x92-type low-density doped region 36 and the nxe2x88x92-type low-density doped region 37 are simultaneously formed to the same depth after the n+-type high-density doped region 31 is formed. Thereafter, the n+-type high-density doped regions 32 and 33 are formed within the nxe2x88x92-type low-density doped regions 36 and 37, respectively, to a depth thinner than the nxe2x88x92-type low-density doped regions 36 and 37.
Therefore, since the nxe2x88x92-type low-density doped region 35 of the channel region 40, the nxe2x88x92-type low-density doped region 36 of the common source region 50 and the nxe2x88x92-type low-density doped region 37 of the drain region 60 are simultaneously formed to the same depth, the nxe2x88x92-type low-density doped region 36 of the common source region 50 extends toward the channel region 40 by a side diffusion. As a result, there is a problem in that a distance margin between the nxe2x88x92-type low-density doped region 36 and the channel region 40 becomes shortened.
As the size of the EEPROM cell is reduced, this problem becomes more serious, and an effective channel length is shortened, leading to a short channel effect. As a result, when a strong electric field is applied between the source region 50 and the drain region 60, a drift current occurs. Such a drift current results in a leakage current, and the threshold voltage distribution becomes bad due to the leakage current. That is, the threshold voltage is varied, whereupon characteristics of the device deteriorate.
To overcome the problems described above, preferred embodiments of the present invention provide a non-volatile memory having an improved threshold voltage dispersion and excellent device characteristics.
The present invention is directed to a non-volatile memory device which includes gate insulating films formed on a semiconductor substrate and spaced apart from each other and a tunnel insulating film formed on the semiconductor substrate and interposed between the adjacent gate insulating films. A memory transistor gate is formed on the tunnel insulating film and the gate insulating film interposing the tunnel insulating film therebetween. A select transistor gate is formed on the gate insulating film spaced apart from the memory transistor gate. A first doped region is formed in a portion of the semiconductor substrate under the memory transistor gate and extending to overlap one end of the select transistor gate. A second doped region is formed in a portion of the semiconductor substrate spaced apart from the first doped region and overlapping one end of the memory transistor opposite to the select transistor gate. A third doped region is formed in a portion of the semiconductor substrate spaced apart from the first doped region and overlapping the other end of the select transistor gate. The second doped region has a low-density doped region and a high-density doped region and is shallower in depth than the first and third doped regions.
In various preferred embodiments of the invention, the low-density doped region and the high-density doped region of the second doped region form a lightly doped drain (LDD) structure. The third doped region has a low-density doped region and a high-density doped region and has a double diffusion structure. The memory transistor gate includes a floating gate, an interlayer insulator and a sense line which are stacked in sequence. The floating gate includes polysilicon, the interlayer insulator includes SiO2 or oxide/nitride/oxide, and the sense line includes polysilicon or polycide. The select transistor gate includes a floating gate, an interlayer insulator and a word line which are stacked in sequence. The tunnel insulating film includes SiO2 or SiON. The first to third doped regions include an nxe2x88x92-type low-density doped region and an n+-type low-density doped region.
The present invention further provides a method of manufacturing a non-volatile memory device. The method of the invention includes: a) providing a semiconductor substrate including gate insulating films, a tunnel insulating film and a first high-density doped region, the gate insulating films being spaced apart from each other, the tunnel insulating film being interposed between the adjacent gate insulating films, the first high-density doped region being formed in a portion of the semiconductor substrate under the tunnel insulating film; b) forming a memory transistor gate and a select transistor gate, the memory transistor gate being formed on the tunnel insulating film and the gate insulating films interposing the tunnel insulating film therebtween, the select transistor gate being formed on the gate insulating film spaced apart from the memory transistor gate; c) forming a first low-density doped region and a second low-density doped region in a channel region, the first low-density doped region abutting the first high-density doped region and extending to overlap one end of the select transistor gate, the second low-density doped region being spaced apart from the first low-density doped region and overlapping the other end of the select transistor gate; d) forming a third low-density doped region, the third low-density doped region being spaced apart from the first high-density doped region and overlapping one end of the memory transistor gate opposite to the select transistor gate; and e) forming a second high-density doped region in a common source region and a third high-density doped region in a drain region, the second high-density doped region being formed in the second low-density doped region, the third high-density region abutting on the third low-density doped region.
In various preferred embodiments of the invention, step (b) includes depositing a first conductive material layer and an interlayer insulator in sequence over the whole surface of the semiconductor substrate; etching simultaneously the first conductive material layer and the interlayer insulator to form a floating gate of the memory transistor gate and a floating gate of the select transistor gate; oxidizing the floating gate to form oxide film on both side walls of the floating gate; depositing a second conductive material layer over the whole surface of the semiconductor substrate; and etching the second conductive material layer to form a sense line of the memory transistor gate and a word line of the select transistor gate.
Step (b) can also include depositing a first conductive material layer and an interlayer insulator in sequence over the whole surface of the semiconductor substrate; etching simultaneously the first conductive material layer and the interlayer insulator to form a floating gate of the memory transistor gate; oxidizing the floating gate to form an oxide film on both side walls of the floating gate; depositing a second conductive material layer over the whole surface of the semiconductor substrate; and etching the second conductive material layer to form a sense line of the memory transistor gate and a word line of the select transistor gate.
The first conductive material layer can includes polysilicon, the interlayer insulator can include SiO2 or ONO, and the second conductive material layer can include polysilicon or polycide. The tunnel insulating film can include SiO2 or SiON.
The first high-density doped region can be formed by ion-implanting a phosphorus ion or an arsenic ion at an accelerating voltage of 40 keV to 100 keV and at a dose of 1.0xc3x971013 atom/cm2 to 1.0xc3x971014 atom/cm2. The second and third high-density doped regions can be formed by ion-implanting an arsenic ion at an accelerating voltage of 40 keV to 60 keV and at a dose of 1.0xc3x971015 atom/cm2 to 5.0xc3x971015 atom/cm2. The first and second low-density doped regions can be formed by ion-implanting a phosphorus ion at an accelerating voltage of 80 keV to 90 keV and at a dose of 1.0xc3x971012 atom/cm2 to 5.0xc3x971013 atom/cm2. The third low-density doped region can be formed by ion-implanting a phosphorus ion or an arsenic ion at an accelerating voltage of 30 keV to 80 keV and at a dose of 1.0xc3x971012 atom/cm2 to 1.0xc3x971013 atom/cm2.
In one embodiment, the method of the invention further comprises, before step (e), depositing an insulating material layer over the whole surface of the semiconductor substrate and etching anisotropically the insulating material layer to from spacers on both side walls of the oxide films. The method can also include, before step (e), depositing an insulating material layer over the whole surface of the semiconductor substrate and etching anisotropically the insulating material layer to form spacers on both side walls of the oxide film.
The EEPROM cell according to the present invention has several advantages. For example, since the low-density doped region of the common source region is formed by a separate process from the low-density doped regions of the channel region and the drain region in a depth shallower than the low-density doped regions of the channel region and the drain region, a side diffusion of the common source region can be reduced. Therefore, an effective channel length of the memory transistor is increased without increasing a size of the EEPROM cell, thereby improving threshold voltage distribution, leading to excellent device characteristics.